By R.S. Soin, F. Maloberti, J. Franca
A wide-ranging e-book with regards to combined analogue electronic ASICs, this identify covers processing
technology, circuit suggestions and development blocks, layout and purposes, and CAD and helping instruments
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Additional info for Analogue-digital ASICs : circuit techniques, design tools and applications
Owing to the short-falls of the above models, Berkeley University have recently developed a MOS model called BSIM . This model has a basis in the level 3 model described above, but has device parameters that are extracted from different geometry devices and then merged to provide a scaling model - however, there are still potential difficulties regarding discontinuities between the linear and saturated regions of operation. The model is usable for devices below lmm. 2 BJT Models In contrast to the MOSFET case, bipolar modelling has not received a great deal of attention over the past decade or so.
6, the base region of the BJT is implanted with boron and diffused. 7 Emitter formation This stage in processing is a critical stage in fabricating the BJT. 7a, an emitter etch through the thin poly-silicon with arsenic and oxide layers (formed in previous gate processing), the deposition of a thick layer of poly-silicon and finally the implantation of the poly-silicon. The critical step is the clean, prior to the deposition of the thick layer of poly-silicon. Control of this clean is important, as the presence of a reasonable thickness of oxide (~ 2nm) can produce a very large BJT current gain (500 or more).
This did, in fact, require a good deal of further engineering work, since the HCMOS process and the BiCMOS process are built on different starting materials. The doping profiles for the CMOS process have also been engineered so that they are compatible with those needed for high performance BJTs - the result of this is that only three extra masks are required to produce the full BiCMOS process. When this is combined with the patented 'collector shunt' structure for the reduction of collector resistance, the whole process is not a great deal more complex to manufacture than the original CMOS process-this is highlighted by Table 1 which compares the two basic process flows.