By Matt Kaufmann, J Strother Moore (auth.), David S. Hardin (eds.)
Design and Verification of Microprocessor platforms for High-Assurance purposes
David S. Hardin
This publication examines a number of modern layout and verification applied sciences which were effectively utilized to microprocessor structures for high-assurance purposes at a number of degrees – from mathematics circuits to microcode to guideline units to working platforms to functions. We specialize in fresh undefined, software program, and procedure designs that experience truly been outfitted and deployed, and have platforms which have been qualified at excessive review coverage degrees, particularly the Rockwell Collins AAMP7G microprocessor (EAL7) and the fairway Hills INTEGRITY-178B separation kernel (EAL6+). The contributing authors to this booklet have endeavored to bring on really new fabric on major, smooth layout and verification efforts; some of the effects defined herein have been received in simple terms in the previous year.
- Offers functional case experiences of the winning program of formal equipment at a number of various degrees of real-world microprocessor approach layout;
- Discusses high-robustness layout innovations that aid formal verification;
- Shows how "Design for Verification" can turn into "Design with Verification", utilizing glossy verification device suites which may without problems import engineering designs;
- Features chapters written through practitioners who've accomplished the top coverage assessment coverage point (EAL) certifications outlined by way of the typical Criteria;
- Formally develops the "GWV" kinfolk of data stream theorems utilized in contemporary EAL6+ and EAL7 certifications;
- Explains how designs expressed in new model-based improvement languages might be analyzed and verified;
- Demonstrates ways that different types of formal verification instruments can be used together to accomplish a last verification result.
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Extra info for Design and Verification of Microprocessor Systems for High-Assurance Applications
4 j C1 4 j C1 Ä mC1 (a) If m ¤ 3, then max 4ı ; 4ı C1 4 ; i Ái 4 j m 1 . (b) If m ¤ 3, then min ıj ; 4ı C1 4 i i Lemma 7. Let d and p be rational numbers, 1 Ä d < 2 and jpj Ä d . Let i and j be integers, 0 Ä i < 4 and 0 Ä j < 32, such that ıi Ä d < ıi C 14 and 1 d mj Ä d . j Ä p < j C 4 . i; j /. Then j4p A Mechanically Verified Commercial SRT Divider 35 Proof. First note that since Ä p Ä d < ıi C j and j 1 4 >p Â Ã 1 ıi C 4 1 > 4 d we may apply Lemma 6. , m 1 Ä 4 p mC1 Ä : d 4 First we establish the upper bound.
In the case n Ä 1, QTooLarge is false and we must show that Q is representable. M. Russinoff ˇ ˇ ˇY ˇ jQj Ä ˇˇ ˇˇ < 2YNB XNBC1 Ä 4: X In the remaining case, YNB XNB Ä w and n > 1. The first of these conditions implies that Á jwk C 1 Ä w C 2I 2n Ä 2 2 thus, by Lemma 3, jQPrej D jQPartn j < 2wC2 ; from which we conclude that jQj Ä 2wC2 . The second condition implies that YNB jY j > 2YNB 2 XNB 2, so 2XNB > jX j; from which we conclude that Q ¤ 0. Thus, if YSign D XSign, then Q > 0, and if YSign ¤ XSign, then Q < 0.
Proof. We consider the three cases separately: (a) In this case, the conclusion holds trivially. X /. If jR0 j D jX j, then R0 D X and R D 0. Y /. Y /. X /. If jR0 j D jX j, then R0 D X and R D 0. Y /. Y /: t u In an SRT implementation, the multiplier mk of Lemma 1 represents a sequence of r bits that are appended to the quotient during the kth iteration. Although not required for the proof of the lemma, it may be assumed that in practice, jmk j < 2r . In particular, in our radix-4 implementation, we have 3 Ä mk Ä 3.